1. Field of the Invention
The present invention is related to power-down biasing circuits, and more particularly, to biasing circuits with power-down capability for applications that require rapid power-up.
2. Related Art
There are a number of applications where rapid power-up by a circuit may be required. For example, in some Wi-Fi applications, the transceiver circuit may be normally “asleep”, but needs to wake up rapidly when necessary. The wakeup time, or the time for the circuit to go from the power-down state to fully functional (power up, or active) state, may be relatively short.
One option is to have a constant biasing current running through the circuit. This is sometimes known as a bleeding current. This increases the wake-up speed, however, particularly for circuits that are only awake a fraction of the time, this approach runs the battery down relatively quickly.
FIG. 1A illustrates a conventional biasing circuit with power-down capability in its active (power-up) state. As shown in FIG. 1A, a current source Iref sources current to a transistor MN101. Two switches SW101 and SW102 control the state of the transistor MN101. In FIG. 1A, 110 is the NMOS current multiplier, and 111 is the PMOS current multiplier. A filtering capacitor CF101 is used to decouple the circuit from noise on a reference current bias line from the power supply Vdd.
NMOS transistors MN102A–MN102N are used as current multipliers. The purpose of the transistors MN102A–MN102N is to distribute current to the mirror circuit(s) 115. The circuit 120, which is the circuit that needs to be supplied with power, is connected to the mirror circuit 115. Each such mirror circuit 115 is connected to a single transistor MN102A–MN102N, as indicated by the dots in the upper portion of FIG. 1A. PMOS transistor MP101 is connected between the power supply Vdd and the transistor MN102N, and is controlled by switches SW103 and SW104. Note that the mirror circuit 115 is not always necessary. The NMOS current mirror embodiment and a PMOS current mirror embodiment are shown cascaded, which is a common circuit arrangement. One could leave out the PMOS embodiment and connect circuit 120 directly above MN102A–N. Alternatively, one could take out the NMOS embodiment replace MN102N with a current mirror Iref sourcing current from MP101.
During power-down, the gate of MN101 is connected to ground, and the drain is open. When the switch SW102 is open, and the switch SW101 is closed, the capacitance of the capacitor CF101, and the properties of current source Iref determine how long the circuit will take to fully power-up. The mirror circuit 115 is replicated for each of the transistors MN102A–MN102N. The purpose of the transistors MP102A–MP102B is to distribute current to the circuit 120. FIG. 1D shows an equivalent circuit for FIG. 1A, where, during power down, Vc moves to potential where the V-I block can generate minimum current (Iout).
FIG. 1C illustrates another conventional power-down circuit, the primary difference of being the location of the switch SW101, which is between the current source Iref and the drain of NMOS transistor MN101. During power-down, the switch SW101 disconnects the current source Iref from the transistor MN101. The gate of the transistor MN101 is connected to ground. The capacitor CF101 here also serves to filter out the noise from the current source Iref. FIG. 1E shows an equivalent circuit for FIG. 1C, where, during power down, Vc moves to potential where the V-I block can generate minimum current (Iout). FIG. 1B shows an equivalent circuit for both FIGS. 1A and 1C, where the V-I block can generate either zero current or minimum current.
FIG. 2 is similar to FIG. 1A, but shows the power-down state compared to FIG. 1A, which shows a power-up state, or active state.
FIG. 3 is an illustration of an equivalent circuit at power-on. In FIG. 3, the transistors MN102 are replaced by a box 303 called current multiplier or control, which receives input from an external source, usually an additional circuit that commands waking up and powering down. Thus, instead of a fixed bias, one can have a controllable bias. The problem with the circuit of FIG. 3 is that each such current mirror 304, such as formed by the transistor MP301 and MP302, adds power-up delay. With an array of such current mirrors 304, the delay becomes quite considerable, and may be unacceptable for particular applications.
Accordingly, what is needed is a power-down biasing circuit that allows for rapid wake-up and is at the same time not affected by high frequency noise on the reference current.